AFEDRI SDR-Net - SDR structure diagram description



AFEDRI SDR-Net is based on same AFEDRI8201 integrated circuit, like AFEDRI SDR of previous revisions, so you can get more information from AFEDRI SDR description page:

Please see the picture below:

There is short block diagram description:

LPF - Low Pass Filter, in default configuration is using as anti-aliasing filter for from DC to ~28MHz (or any frequency located below Nyquist limit).

Can be easily replaced by band-pass filter (BPF) for desired band in under-sampling acquisition mode when received signal is lying over Nyquist frequency (for example 50MHz, 70MHz band, 108MHz). I tested undersampling mode with this receiver on WFM band (88-108MHz), there is some degradation in sensitivity, so it will be better to add external low noise amplifier (LNA) for DX SWL on WFM band.

VGA - Variable Gain Amplifier, it is built using AD8369 IC from Analog Devices, and adjusted in in this design to give amplification/attenuation of input signal from -10dB up to 35dB.

RF Switch - is used in VHF/SHF SDR versions to switch analog  signal path between HF VGA and VHF Front End.

VHF/SHF Front End - Analog Font End chip for VHF/SHF band, based on R820T2 chip (like in RTL dongles)

HPF - High Pass filter for VHF/SHF bands R820T2 front End chip

TCXO - Thermal Compensated Crystal +/- 0.5ppm Oscillator, used as reference oscillator for R820T2 Front End chip

VHF/SHF Power Switch - used to switch on or off 3.3V voltage for R820T2 Front End (when VHF/SHF band is enabled)

DDC Front End - i.e Analog Front End is built on AFEDRI8201PBF integrated circuit, it is heart of SDR, that providing Input RF signal ADC sampling, mixing and digital filtering, base-band signal data is outputs through specific serial interface, that very similar to I2S but not 100% compatible, for example used in my design CPU, need external help from CPLD, to accept data incoming data. More information about you can find in datasheet. Please pay attention that this device is not recommended  by Texas Instruments for new design, but there is many way to achieve this integrated cuicuits from different sources. And I am sure HAM radio society can use it in their applications.   For example I have some quantity of AFEDRI8201PBF in my stock.

FPGA - main function of this device to convert AFEDRI8201 base-band (output data) serial protocol to Serial or Parallel data transfer protocol, that can be received by used in design CPU.

CPU - it ARM Cortex-M3 architecture microprocessor - STM32F207VC (or STM32F207VC), from ST Microelectronics, it controls Analog Frond End by additional SPI control channel, receive processed base-band data from Front End and transfer it to PC using Network interface or USB link and software USB Audio Device and HID device emulation.

Ethernet (RMII PHY) - Ethernet physical layer transceiver, working as interface between LAN (network) and CPU

Power Supply - Whole receiver is supplied from 5V voltage of USB line, and there is three voltages +1.8V -digital, 3.3- digital and 3.3V analog, that generated from single supply voltage.

External Power Supply - Is used as alternative power supply from external DC source, like battery or transceiver power supply, it is  switched DC/DC power supply the SDR. Can work from external sources that gives DC voltage in range 7.5V-15V

Power Switch - automatically switches between USB or external voltage source.

Optional LCD - there is optional parallel LCD interface exists in SDR, LCD is not supported by current firmware yet, cause I am not sure do someone really need it, but can be easily implemented in the future on user request.

The full AFEDRI SDR-Net schematic  can be found on my Download page.